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RTL设计工程师岗位职责
IC设计工程师(RTL工程师) 工作內容
- RTL coding for digital IP design
-Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers - Responsible for ASIC project management and coordination among internal supporting groups - Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation - Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
-職務類別:數位IC設計工程師
-管理責任:不需負擔管理責任
-出差外派:無需外派
-可上班日:不限
-需求人數:5人
條件要求
-接受身份:上班族
-工作經歷:不拘
-學歷要求:大學、碩士
-科系要求:電機電子工程相關、資訊工程相關
-語文條件:不拘
-擅長工具:不拘
-工作技能:不拘
-其他條件:俱有advanced node process經驗優先
1. BS or MS degree in EE or CS related.
2. Experienced in chip design flow and chip implementation flow 3. Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools 4. Familiar with DFT related flow and utilities is a plus 5. Interested in communicating with people 工作內容
- RTL coding for digital IP design
-Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers - Responsible for ASIC project management and coordination among internal supporting groups - Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation - Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
-職務類別:數位IC設計工程師
-管理責任:不需負擔管理責任
-出差外派:無需外派
-可上班日:不限
-需求人數:5人
條件要求
-接受身份:上班族
-工作經歷:不拘
-學歷要求:大學、碩士
-科系要求:電機電子工程相關、資訊工程相關
-語文條件:不拘
-擅長工具:不拘
-工作技能:不拘
-其他條件:俱有advanced node process經驗優先
1. BS or MS degree in EE or CS related.
2. Experienced in chip design flow and chip implementation flow 3. Familiar with EDA tools including PrimeTime, Debussy, Verilog-XL, Design Compiler, and formal verification tools 4. Familiar with DFT related flow and utilities is a plus 5. Interested in communicating with people